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vnb10n07/k10n07fm vnp10n07fi/VNV10N07 "omnifet": fully autoprotected power mosfet ? june 1998 block diagram ( * ) type v clamp r ds(on) i lim vnb10n07 vnk10n07fm vnp10n07fi VNV10N07 70 v 70 v 70 v 70 v 0.1 w 0.1 w 0.1 w 0.1 w 10 a 10 a 10 a 10 a n linear current limitation n thermal shut down n short circuit protection n integrated clamp n low current drawn from input pin n diagnostic feedback through input pin n esd protection n direct access to the gate of the power mosfet (analog driving) n compatible with standard power mosfet description the vnb10n07, vnk10n07fm, vnp10n07fi and VNV10N07 are monolithic devices made using stmicroelectronics vipower m0 technology, intended for replacement of standard power mosfets in dc to 50 khz applications. built-in thermal shut-down, linear current limitation and overvoltage clamp protect the chip in harsh enviroments. fault feedback can be detected by monitoring the voltage at the input pin. 1 10 powerso-10 1 3 1 2 3 isowatt220 d2pak to-263 sot82-fm ( * ) powerso-10 pin configuration : input = 6,7,8,9,10; source = 1,2,4,5; drain = tab 1/14
absolute maximum rating symbol parameter value unit powerso-10 d2pak sot-82fm isowatt220 v ds drain-source voltage (v in = 0) internally clamped v v in input voltage 18 v i d drain current internally limited a i r reverse dc output current -14 a v esd electrostatic discharge (c= 100 pf, r=1.5 k w ) 2000 v p tot total dissipation at t c = 25 o c 50 9.5 31 w t j operating junction temperature internally limited o c t c case operating temperature internally limited o c t stg storage temperature -55 to 150 o c thermal data isowatt220 powerso-10 sot82-fm d2pak r thj-case thermal resistance junction-case max 4 2.5 13 2.5 o c/w r thj-amb thermal resistance junction-ambient max 62.5 50 100 62.5 o c/w electrical characteristics (t case = 25 o c unless otherwise specified) off symbol parameter test conditions min. typ. max. unit v clamp drain-source clamp voltage i d = 200 ma v in = 0 607080 v v clth drain-source clamp threshold voltage i d = 2 ma v in = 0 55 v v incl input-source reverse clamp voltage i in = -1 ma -1 -0.3 v i dss zero input voltage drain current (v in = 0) v ds = 13 v v in = 0 v ds = 25 v v in = 0 50 200 m a m a i iss supply current from input pin v ds = 0 v v in = 10 v 250 500 m a on ( * ) symbol parameter test conditions min. typ. max. unit v in(th) input threshold voltage v ds = v in i d + ii n = 1 ma 0.8 3 v r ds(on) static drain-source on resistance v in = 10 v i d = 5 a v in = 5 v i d = 5 a 0.1 0.14 w w vnb10n07-vnk10n07fm-vnp10n07fi-VNV10N07 2/14
electrical characteristics (continued) dynamic symbol parameter test conditions min. typ. max. unit g fs ( * ) forward transconductance v ds = 13 v i d = 5 a 6 8 s c oss output capacitance vds = 13 v f = 1 mhz v in = 0 350 500 pf switching (**) symbol parameter test conditions min. typ. max. unit t d(on) t r t d(off) t f turn-on delay time rise time turn-off delay time fall time v dd = 15 v i d = 5 a v gen = 10 v r gen = 10 w (see figure 3) 50 80 230 100 100 160 400 180 ns ns ns ns t d(on) t r t d(off) t f turn-on delay time rise time turn-off delay time fall time v dd = 15 v i d = 5 a v gen = 10 v r gen = 1000 w (see figure 3) 600 0.9 3.8 1.7 900 2 6 2.5 ns m s m s m s (di/dt) on turn-on current slope v dd = 15 v i d = 5 a v in = 10 v r gen = 10 w 60 a/ m s q i total input charge v dd = 12 v i d = 5 a v in = 10 v 30 nc source drain diode symbol parameter test conditions min. typ. max. unit v sd ( * ) forward on voltage i sd = 5 a v in = 0 1.6 v t rr ( ** ) q rr ( ** ) i rrm ( ** ) reverse recovery time reverse recovery charge reverse recovery current i sd = 5 a di/dt = 100 a/ m s v dd = 30 v t j = 25 o c (see test circuit, figure 5) 125 0.3 4.8 ns m c a protection symbol parameter test conditions min. typ. max. unit i lim drain current limit v in = 10 v v ds = 13 v v in = 5 v v ds = 13 v 7 7 10 10 14 14 a a t dlim ( ** ) step response current limit v in = 10 v v in = 5 v 20 50 30 80 m s m s t jsh ( ** ) overtemperature shutdown 150 o c t jrs ( ** ) overtemperature reset 135 o c i gf ( ** ) fault sink current v in = 10 v v ds = 13 v v in = 5 v v ds = 13 v 50 20 ma ma e as ( ** ) single pulse avalanche energy starting t j = 25 o c v dd = 20 v v in = 10 v r gen = 1 k w l = 10 mh 0.4 j ( * ) pulsed: pulse duration = 300 m s, duty cycle 1.5 % ( ** ) parameters guaranteed by design/characterization vnb10n07-vnk10n07fm-vnp10n07fi-VNV10N07 3/14
during normal operation, the input pin is electrically connected to the gate of the internal power mosfet. the device then behaves like a standard power mosfet and can be used as a switch from dc to 50 khz. the only difference from the users standpoint is that a small dc current (i iss ) flows into the input pin in order to supply the internal circuitry. the device integrates: - overvoltage clamp protection: internally set at 70v, along with the rugged avalanche characteristics of the power mosfet stage give this device unrivalled ruggedness and energy handling capability. this feature is mainly important when driving inductive loads. - linear current limiter circuit: limits the drain current id to ilim whatever the input pin voltage. when the current limiter is active, the device operates in the linear region, so power dissipation may exceed the capability of the heatsink. both case and junction temperatures increase, and if this phase lasts long enough, junction temperature may reach the overtemperature threshold t jsh . - overtemperature and short circuit protection: these are based on sensing the chip temperature and are not dependent on the input voltage. the location of the sensing element on the chip in the power stage area ensures fast, accurate detection of the junction temperature. overtemperature cutout occurs at minimum 150 o c. the device is automatically restarted when the chip temperature falls below 135 o c. - status feedback: in the case of an overtemperature fault condition, a status feedback is provided through the input pin. the internal protection circuit disconnects the input f rom the gate and connects it instead to ground via an equivalent resistance of 100 w . the failure can be detected by monitoring the voltage at the input pin, which will be close to ground potential. additional features of this device are esd protection according to the human body model and the ability to be driven from a ttl logic circuit (with a small increase in r ds(on) ). protection features vnb10n07-vnk10n07fm-vnp10n07fi-VNV10N07 4/14
thermal impedance for isowatt220 derating curve transconductance thermal impedance for d2pak / powerso-10 output characteristics static drain-source on resistance vs input voltage vnb10n07-vnk10n07fm-vnp10n07fi-VNV10N07 5/14
static drain-source on resistance input charge vs input voltage normalized input threshold voltage vs temperature static drain-source on resistance capacitance variations normalized on resistance vs temperature vnb10n07-vnk10n07fm-vnp10n07fi-VNV10N07 6/14
normalized on resistance vs temperature turn-on current slope turn-off drain-source voltage slope turn-on current s lope turn-off drain-source voltage slope switching time resistive load vnb10n07-vnk10n07fm-vnp10n07fi-VNV10N07 7/14
switching time resistive load current limit vs junction temperature source drain diode forward characteristics switching time resistive load step response current limit vnb10n07-vnk10n07fm-vnp10n07fi-VNV10N07 8/14
fig. 2: unclamped inductive waveforms fig. 3: switching times test circuits for resistive load fig. 4: input charge test circuit fig. 1: unclamped inductive load test circuits fig. 5: test circuit for inductive load switching and diode recovery times fig. 6: waveforms vnb10n07-vnk10n07fm-vnp10n07fi-VNV10N07 9/14
dim. mm inch min. typ. max. min. typ. max. a 4.3 4.6 0.169 0.181 a1 2.49 2.69 0.098 0.106 b 0.7 0.93 0.027 0.036 b2 1.25 1.4 0.049 0.055 c 0.45 0.6 0.017 0.023 c2 1.21 1.36 0.047 0.053 d 8.95 9.35 0.352 0.368 e 10 10.28 0.393 0.404 g 4.88 5.28 0.192 0.208 l 15 15.85 0.590 0.624 l2 1.27 1.4 0.050 0.055 l3 1.4 1.75 0.055 0.068 l2 l3 l b2 b g e a c2 d c a1 p011p6/c to-263 (d2pak) mechanical data vnb10n07-vnk10n07fm-vnp10n07fi-VNV10N07 10/14
dim. mm inch min. typ. max. min. typ. max. a 2.85 3.05 1.122 1.200 a1 1.47 1.67 0.578 0.657 b 0.40 0.60 0.157 0.236 b1 1.4 1.6 0.551 0.630 b2 1.3 1.5 0.511 0.590 c 0.45 0.6 0.177 0.236 d 10.5 10.9 4.133 4.291 e 2.2 2.8 0.866 1.102 e 7.45 7.75 2.933 3.051 l 15.5 15.9 6.102 6.260 l1 1.95 2.35 0.767 0.925 p032r sot82-fm mechanical data vnb10n07-vnk10n07fm-vnp10n07fi-VNV10N07 11/14
dim. mm inch min. typ. max. min. typ. max. a 4.4 4.6 0.173 0.181 b 2.5 2.7 0.098 0.106 d 2.5 2.75 0.098 0.108 e 0.4 0.7 0.015 0.027 f 0.75 1 0.030 0.039 f1 1.15 1.7 0.045 0.067 f2 1.15 1.7 0.045 0.067 g 4.95 5.2 0.195 0.204 g1 2.4 2.7 0.094 0.106 h 10 10.4 0.393 0.409 l2 16 0.630 l3 28.6 30.6 1.126 1.204 l4 9.8 10.6 0.385 0.417 l6 15.9 16.4 0.626 0.645 l7 9 9.3 0.354 0.366 ? 3 3.2 0.118 0.126 l2 a b d e h g l6 f l3 g1 123 f2 f1 l7 l4 isowatt220 mechanical data p011g vnb10n07-vnk10n07fm-vnp10n07fi-VNV10N07 12/14
dim. mm inch min. typ. max. min. typ. max. a 3.35 3.65 0.132 0.144 a1 0.00 0.10 0.000 0.004 b 0.40 0.60 0.016 0.024 c 0.35 0.55 0.013 0.022 d 9.40 9.60 0.370 0.378 d1 7.40 7.60 0.291 0.300 e 9.30 9.50 0.366 0.374 e1 7.20 7.40 0.283 0.291 e2 7.20 7.60 0.283 0.300 e3 6.10 6.35 0.240 0.250 e4 5.90 6.10 0.232 0.240 e1.27 0.050 f 1.25 1.35 0.049 0.053 h 13.80 14.40 0.543 0.567 h0.50 0.002 l 1.20 1.80 0.047 0.071 q1.70 0.067 a 0 o 8 o detail "a" plane seating a l a1 f a1 h a d d1 = = = = = = e4 0.10 a e1 e3 c q a = = b b detail "a" seating plane = = = = e2 6 10 5 1 e b he m 0.25 = = = = 0068039-c powerso-10 mechanical data vnb10n07-vnk10n07fm-vnp10n07fi-VNV10N07 13/14
information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsib ility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rig hts of stmicroelectroni cs. spe cification mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previou sly supplied. st microelectronics products are not authorized for use as critical compone nts in life support devices or systems without express written approval of stmicroelectron ics. the st logo is a trademark of s tmicroelectronics ? 1998 stmicroelectronics C printed in italy C all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - france - germany - italy - japan - korea - malaysia - malta - mexico - morocco - the neth erlands - singapore - spain - sweden - switzerland - taiwan - thailand - united kingdom - u.s.a. . vnb10n07-vnk10n07fm-vnp10n07fi-VNV10N07 14/14

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